Short channel characteristics of quasi-single-drain MOSFETs

It is clearly demonstrated that source/drain (S/D) elevation is remarkably effective to suppress the short channel effect against the shrinkage of gat e sidewall spacers in MOSFETs, Even if the gate sidewall width is reduced t o as very thin as 15 nm, the short channel effect is effectively suppressed by means of the highly elevated S/D regions (80 nm in the present case), t hough the characteristics of conventional MOSFETs are drastically degraded. This result is explained in terms of the fact that the serious influence d ue to the deep S/D implantation is suppressed by the formation of a quasi-s ingle-drain configuration. Furthermore, the parasitic S/D resistance decrea se, which will bring about drivability enhancement, was observed for reduct ion in the sidewall width. These favorable experimental results may indicat e the definite necessity of elevated SID engineering for future ultrashort MOSFETs.