Full-wave PEEC time-domain method for the modeling of on-chip interconnects

With the advances in the speed of high-performance chips, inductance effect s in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especia lly impacted by inductance. Several difficult aspects have to be overcome t o obtain valid waveforms for problems where inductances contribute signific antly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simult aneously, In this paper, we show that a full-wave partial element equivalen t circuit method, which includes the delays among the partial elements, lea ds to an efficient solver enabling the analysis of large meaningful problem s. Applying this method to several examples leads to helpful insights for r ealistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are cr itical for the design of critical on-chip interconnects.