Reduction of power consumption in scan-based circuits during test application by an input control technique

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application time. The basic idea is to iden tify an input control pattern (CP) for a full-scan circuit such that by app lying the pattern to the primary inputs of the circuit during the scan oper ation, the switching activity in the combinational part can be reduced or e ven eliminated. A D-algorithm-like CP generator is developed to generate th e CP, This input control technique can be utilized together with the existi ng vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve 22.3 7% of average improvement by redoing the experiments in previous work using our test sets, while 34.23% average improvement can be achieved if the inp ut control technique is employed after the latch ordering and vector orderi ng techniques.