Dynamic binary translation and optimization

We describe a VLIW architecture designed specifically as a target for dynam ic compilation of an existing instruction set architecture. This design app roach offers the simplicity and high performance of statically scheduled ar chitectures, achieves compatibility with an established architecture, and m akes use of dynamic adaptation. Thus, the original architecture is implemen ted using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits r untime profile information to optimize translations so as to extract instru ction level parallelism. This work reports different design trade-offs in t he DAISY system and their impact on final system performance. The results s how high degrees of instruction parallelism with reasonable translation ove rhead and memory usage.