LOW-VOLTAGE MANCHESTER ADDER DESIGN

A low voltage dynamic Manchester adder design is presented, with a cri tical delay path operating at a higher voltage level. This voltage lev el is generated on-chip using a bootstrapping circuit. The goal of thi s design is to maintain the delay of its worst-case path, comparable t o-the design having a higher supply voltage, while operating the rest of the circuit at a lower supply voltage, thus consuming less overall power. A SPICE simulation is performed to verify the design.