DESIGN AND IMPLEMENTATION OF DUAL PROCESSOR BLOCK WITH SHARED EXTERNAL CACHE MEMORY

The availability of low cost, high performance microprocessors has led to various designs of shared memory multiprocessor systems. As a resu lt, commercial products which are based on shared memory have been pro liferated. Such a multiprocessor system is heavily influenced by the s tructure of memory system and it is not difficult to find that most co nfigurations include local cache memories. The more processors a syste m carries, the larger local cache memory is needed to maintain the tra ffic to and from the shared memory at reasonable level. The implementa tion of local cache memories, however, is not a simple task because of environmental limitations. In particular, the general lack of board s pace availability presents a formidable problem. A cache memory system usually needs space mostly to support its complex control logic circu its for the cache itself and network interfaces like snooping logic ci rcuits for shared bus. Although packaging can be made denser to reduce system size, there are still multiple processors per board. It requir es a more area-efficient cache memory architecture. This pager present s a design of shared cache for dual processor board of bus-based symme tric multiprocessors. The design and implementation issues are describ ed first and then the evaluation and measurement results are discussed . The shared cache proposed in this paper has been determined to be qu ite area-efficient without the significant loss of throughput and scal ability. It has been implemented as a plug-in unit for TICOM, a preval ent commercial multiprocessor system. (C) 1997 Elsevier Science B.V.