BOAR - AN ADVANCED HW SW COEMULATION ENVIRONMENT FOR DSP SYSTEM-DEVELOPMENT/

Citation
J. Isoaho et al., BOAR - AN ADVANCED HW SW COEMULATION ENVIRONMENT FOR DSP SYSTEM-DEVELOPMENT/, Microprocessors and microsystems, 20(10), 1997, pp. 607-615
Citations number
20
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture","Computer Science Theory & Methods
ISSN journal
01419331
Volume
20
Issue
10
Year of publication
1997
Pages
607 - 615
Database
ISI
SICI code
0141-9331(1997)20:10<607:B-AAHS>2.0.ZU;2-#
Abstract
The BOAR emulation system is targeted to hardware/software (HW/SW) cod evelopment of advanced embedded DSP and telecom systems. The challenge of the BOAR system is efficient customization of programmable hardwar e, and dedicated partitioning routine to target applications and struc tures, which allows quite high overall system performance. The system allows multiple configurations for communication between processors an d field programmable gate arrays (FPGAs) making the BOAR system an eff icient tool for real-time HW/SW coverification. The reprogrammable har dware of the emulation tool is based on four Xilinx 4000-series device s, two Texas TMS320C50 signal processors and one Motorola MC68302 micr ocontroller. With current devices the BOAR hardware provides approxima tely 40-70 kgates of logic capacity in DSP applications. The emulation capacity can be expanded by connecting several similar boards in chai n. The system has also a versatile internal reprogrammable test enviro nment for test bench development, performance evaluations and design d ebugging. The logic development environment is based on the Synopsys s ynthesis tools and an automatic design management software, which perf orms resource mapping and performance-driven design partitioning betwe en FPGAs. The emulation hardware is currently connected to logic and s oftware development environments via an RS-232C bus. The BOAR emulatio n system has been found a very efficient platform for real-life protot yping of different types of DSP algorithms and systems, and validating correct functionality of a VHDL macro library. (C) 1997 Elsevier Scie nce B.V.