The degradation of p-MOSFETs under off-state stress

Citation
Cy. Yang et al., The degradation of p-MOSFETs under off-state stress, MICROELEC J, 32(7), 2001, pp. 587-591
Citations number
13
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONICS JOURNAL
ISSN journal
00262692 → ACNP
Volume
32
Issue
7
Year of publication
2001
Pages
587 - 591
Database
ISI
SICI code
0026-2692(200107)32:7<587:TDOPUO>2.0.ZU;2-P
Abstract
The hot carrier effects under off-state stress mode (V-gs = 0 V; V-ds < 0 V ) have been investigated on 9 nm p-MOSFETs with channel length varying from 1.025 to 0.525 mum. Both on- and off-state currents are discussed in this paper. It is found that the off-state leakage current will decrease after h igher stressing voltage, which is induced by charge injection occurring clo se to the drain junction. However, the leakage current will increase after lower stressing voltage because of the newly generated interface traps. It is also found that the on-state saturation current and threshold voltage de graded significantly with stress time, which we believe is due to the charg es injected near the gate-drain overlapping region and/or the stress-induce d interface trap generation. The degradation of I-dsat can be expressed as a function of the product of the gate current (I-g) times the number of cha rges injected into the gate oxide (Q(inj)) in a simple power law. Finally, a lifetime prediction model based on the degradation of I-dsat is proposed. (C) 2001 Published by Elsevier Science Ltd.