Nanoscale Coulomb blockade memory and logic devices

This paper gives a brief review of our recent work done in the area of nano metre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent proble ms to conventional semiconductor devices. We introduce multiple-tunnel junc tions (MTJs), naturally formed in heavily doped semiconductor nanowires, as a key building block for our CB devices. For memory applications, the hybr id MTJ/MOS cell architecture is described, and its high-speed RAM operation is investigated. For logic applications the binary decision diagram logic is discussed as a suitable architecture for low-gain Mn transistors.