3-D ICs: A novel chip design for improving deep-submicrometer interconnectperformance and systems-on-chip integration

Performance of deep-submicrometer ver large scale integrated (VLSI) circuit s is being increasingly dominated by the interconnects due to decreasing wi re pitch and increasing die size. Additionally heterogeneous integration of different technologies in one single chip is becoming increasingly desirab le, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and desi gn methodologies and presents a novel three-dimensional (3-D) chip design s trategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologie s to realize a system-on-a-chip (SoC) design. A comprehensive analytical tr eatment of these 3-D ICs has been presented and it has been shown that by s imply divining a planar chip into separate blocks, each occupying a separat e physical level interconnected by short and vertical interlayer interconne cts (VILICs), significant improvement in performance and reduction in wire- limited chip area can he achieved. without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution amon g different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs aris ing due to power dissipation problems has been analyzed and an analytical m odel has been presented to estimate the temperatures of the different activ e layers. It is demonstrated that advancement in hear sinking technology wi ll be necessary in order to extract maximum performance from these chips. I mplications of 3-D device architecture on several design is sues have also been discussed with especial attention to SoC design strategies. Finally, s ome of the promising technologies for manufacturing 3-D ICs have been outli ned.