Parasitic extraction: Current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (small er feature size) in deep submicrometer (DSM) designs, interconnect parasiti c effects are increasingly becoming more important. This paper first survey s the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interco nnect modeling, model order reduction, delay calculation, and signal integr ity issues such as crosstalk. Some future trends on parasitic extraction, m odel reduction and interconnect modeling are discussed and a fairly complet e list of references is given.