Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

We start with a detailed analysis of the communication issues in today's sy mmetric multiprocessor (SMP) architectures to study the benefits of impleme nting optical interconnects (OI) in these machines. We show that the transm ission of block addresses is the most critical communication bottleneck of future large SMPs owing to the need to preserve the coherence of data dupli cated in caches. An address transmission bandwidth as high as 200-300 Gb/s may be necessary in ten years from now; this requirement will represent a d ifficult challenge for shared electric buses. In this context we suggest th e introduction of simple point-to-point OIs for a SMP cache-coherent switch , i.e., for a VLSI switch that would emulate the shared-bus function. The o peration might require as much as 10,000 input-outputs (IOs) to connect 100 processors, particularly if one maintains the present parallelism of trans missions to preserve a large bandwidth and a short memory access latency. T he interest for OIs comes from the potential increase of the transmission f requency and from the possible integration of such a high density of IOs on top of electronic chips to overcome packaging issues. Then we consider the implementation of an optical bus that is a multipoint optical line involvi ng more optical technology. This solution allows multiple simultaneous acce sses to the bus, but the preservation of the coherence of caches can no lon ger be maintained with the usual fast snooping protocols. (C) 2001 Optical Society of America.