High-throughput coherence control and hardware messaging in Everest

Everest is an architecture for high-performance cache coherence and message passing in partitionable distributed shared-memory systems that use commod ity shared multiprocessors (SMPs) as building blocks. The Everest architect ure is intended for use in designing future IBM sewers using either PowerPC ((R)) or Intel((R)) processors. Everest provides high-throughput protocol h andling in three dimensions: multiple protocol engines, split request-respo nse handling, and pipelined design. It employs an efficient directory subsy stem design that matches the directory-access throughput requirement of hig hperformance protocol engines. A new directory design called the complete a nd concise remote (CCR) directory, which contains roughly the same amount o f memory as a sparse directory but retains the benefits of a full-map direc tory, is used. Everest also supports system partitioning and provides a tig htly integrated facility for secure, high-performance communication between partitions. Simulation results for both technical and commercial applicati ons exploring some of the Everest design space are presented. The results s how that the features of the Everest architecture can have significant impa ct on the performance of distributed shared-memory sewers.