IBM Memory Expansion Technology (MXT)

Several technologies are leveraged to establish an architecture for a low-c ost, highperformance memory controller and memory system that more than dou ble the effective size of the installed main memory without significant add ed cost. This architecture is the first of its kind to employ real-time mai n-memory content compression at a performance competitive with the best the market has to offer, A large low-latency shared cache exists between the p rocessor bus and a content-compressed main memory. Highspeed, low-latency h ardware performs realtime compression and decompression of data traffic bet ween the shared cache and the main memory. Sophisticated memory management hardware dynamically allocates main-memory storage in small sectors to acco mmodate storing the variable-sized compressed data without the need for "ga rbage" collection or significant wasted space due to fragmentation. Though the main-memory compression ratio is limited to the range 1:1-64:1, typical ratios range between 2:1 and 6:1, as measured in "real-world" system appli cations.