Unified VLSI systolic array design for LZ data compression

Hardware implementation of data compression algorithms is receiving increas ing attention due to exponentially expanding network traffic and digital da ta storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compressio n. A VLSI chip implementing our optimal linear array is fabricated and test ed, The proposed array architecture is scalable. Also, multiple chips (line ar arrays) can be connected in parallel to implement the parallel array str ucture and provide a proportional speedup.