A reconfigurable multifunction computing cache architecture

A considerable portion of a microprocessor chip is dedicated to cache memor y. However, not all applications need all the cache storage all the time, e specially the computing bandwidth-limited applications, In addition, some a pplications have large Embedded computations with a regular structure. Such applications may be able to use additional computing resources. If the unu sed portion of the cache could serve these computation needs, the on-chip r esources would be utilized more efficiently, This presents an opportunity t o explore the reconfiguration of a part of the cache memory for computing. Thus, we propose adaptive balanced computing (ABC)dynamic resource configur ation on demand From application-between memory and computing resources. In this paper, we present a cache architecture to convert a cache into a comp uting unit for either of the following two structured computations: finite impulse response and discrete/inverse discrete eosine transform. In order t o convert a cache memory to a function unit, we include additional logic to embed multibit output lookup tables Into the cache structure. The experime ntal results show that the reconfigurable module improves the execution tim e of applications with a large number of data elements by a factor as high as 50 and 60.