An educational tool for testing caches on symmetric multiprocessors

In this article, we present a simulator for cache memory systems on symmetr ic multiprocessors. This simulator is called SMPCache. It has a full graphi c and user-friendly interface, and it operates on PC systems with Windows. The simulator has been conceived as a tool for the teaching of cache memori es on multiprocessors systems. This tool is very useful to evaluate and und erstand different design alternatives: the number of processors, the cache coherence protocols, schemes for bus arbitration, mapping, replacement poli cies, cache size, memory block size, etc. Our experiences in the last three years have demonstrated to us the benefits of the simulator for teaching p urposes. (C) 2001 Elsevier Science B.V. All rights reserved.