Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

We combine a self-organizing diblock copolymer system with semiconductor pr ocessing to produce silicon capacitors with increased charge storage capaci ty over planar structures. Our process uses a diblock copolymer thin film a s a mask for dry etching to roughen a silicon surface on a 30 nm length sca le, which is well below photolithographic resolution limits. Electron micro scopy correlates measured capacitance values with silicon etch depth, and t he data agree well with a geometric estimate. This block copolymer nanotemp lating process is compatible with standard semiconductor processing techniq ues and is scalable to large wafer dimensions. (C) 2001 American Institute of Physics.