The architecture design for a high-speed front-end video prefiltering is de
scribed, this being part of an effort to develop a realtime range-doppler d
igital SAR processor to produce image maps of the scanned area immediately
as raw data are collected. The evolved architecture consists of three-dimen
sionally interconnected planes of modified transverse FIR parallel tapped e
lements. Both the range and azimuth prefilterings are performed simultaneou
sly in a continuous input-output flow without the need to consider corner t
urning. The computation load has been reduced to one complex multiplication
and two complex additions.