Si substrate resistivity design for on-chip matching circuit based on electro-magnetic simulation

For on-chip matching Si-MMIC fabricated on a conventional low resistivity S i substrate, the loss of on-chip inductors is quite high due to the dielect ric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By us ing electromagnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and tile resistivity of Si substra te is: discussed. Based on tile simulated results, the resistivity of Si su bstrate is: designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extr action of equivalent circuit model parameters of the fabricated on-chip spi ral inductors and the measurement of the fabricated on-chip matching Si-MMI C LNA's.