An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths

Authors
Kranitis, N Paschalis, A Gizopoulos, D Psarakis, M Zorian, Y
Citation
N. Kranitis et al., An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths, J ELEC TEST, 17(2), 2001, pp. 97-107
Citations number
17
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
ISSN journal
09238174 → ACNP
Volume
17
Issue
2
Year of publication
2001
Pages
97 - 107
Database
ISI
SICI code
0923-8174(200104)17:2<97:AEDBSF>2.0.ZU;2-U
Abstract
In this paper an effective Built-In Self-Test (BIST) scheme for the shifter -accumulator pair (accumulation performed either by an adder or an ALU) whi ch appears very often in embedded processor, microprocessor or DSP datapath s is introduced. The BIST scheme provides very high fault coverage (> 99%) with respect to the stuck-at fault model for any datapath width with a regu lar, very small and counter-generated deterministic test set, as it is veri fied by a comprehensive set of experiments.