Fault models and test generation for OpAmp circuits - The FFM

The analog VLSI technology processes are reaching the matureness, neverthel ess, there is a big constraint, regarding their use on complex electronic p roducts: "the test". The "Design for Testability" paradigm was developed to permit the test plan implementation early in the design cycle. However to succeed onto this strategy, the fault simulation should be carried out in o rder to evaluate appropriate test patterns, fault grade and so forth. Conse quently adequate fault models must be established. Due to the lack of fault models, suitable to fault simulation on OpAmps, we propose in this work a methodology for Functional Fault Modeling-FFM, and some methods for test ge neration. A fault dictionary for OpAmps is built and a procedure for compac t test vector construction is proposed. The results have shown that high le vel OpAmp requirements, as slew-rate, common mode rejection ration etc., ca n be checked by this approach with good compromise between the fault modeli ng problem, the analog nature of the circuit and the circuit complexity by itself.