A low-cost BIST architecture for linear histogram testing of ADCs

This paper investigates the viability of an ADC BIST scheme for implementin g the histogram test technique. An original approach is developed to extrac t the ADC parameters from the histogram with a minimum area overhead. In pa rticular, it is shown that the choice of a triangle-wave input signal combi ned with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.