Synthesis of an 8051-like micro-controller tolerant to transient faults

This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a p articular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the micro-controller behavior was perfor med. Furthermore, a fault tolerant technique was implemented in a version o f the 8051. The VHDL description of the fault-tolerant microprocessor was p rototyped in a FPGA environment and results in terms of area overhead, leve l of protection and performance penalties are discussed.