Fully relaxed Si0.7Ge0.3 buffers grown on patterned silicon substrates forhetero-CMOS transistors

For a successful fabrication of hetero-CMOS transistors the compatibility o f the epitaxial growth of the heterostructures with the standard CMOS proce ss is an important factor. A very promising integration approach utilizes t he realization of heterostructures in a limited area, so-called differentia l epitaxy. In this paper, we report on new results of fully strain-relaxed SiGe buffers (SRB) with a thickness of about 750 nm, i.e. on the order of t he thickness of the field oxide in the standard CMOS technology. The SiGe S RB layers completed by active device layer stacks were grown by several gro wth concepts, linearly and step-graded buffers and in comparison a method u sing a low-temperature epitaxial Si (LTE-Si) starting layer. The influence of lateral dimensions and of the different growth concepts on the surface m orphology, relaxation and defect density has been investigated. Differentia l interference contrast (DIC) micrographs and atomic force measurements (AF M) were applied to characterize the surface topography. The relaxation meas urements in the patterned areas were performed using micro-Raman spectrosco py. The analysis of the dislocations was carried out by transmission electr on microscopy (TEM). Two main results should be emphasized: Full relaxation (also in the small window) was only achieved for the SiGe buffer with 50-n m LTE-Si and TEM images show different dislocation structures for a graded buffer and the buffer with 50-nm LTE-Si. (C) Kluwer Academic Publishers.