Modelling background charge rearrangements near single-electron transistors as a Poisson process

Background charge rearrangements in metallic single-electron transistors ar e modelled in two-level tunnelling systems as a Poisson process with a scal e parameter as only variable. The model explains the recent observation of asymmetric Coulomb bloc ade peak spacing distributions in metallic single-e lectron transistors. These distributions are consistent with charge trappin g processes within impurities located between transistor island and gate. F rom the scale parameter determined, we estimate the average size of the tun nelling systems, their density of states, and the height of their energy ba rrier.