A HYBRID RADIX-4 RADIX-8 LOW-POWER SIGNED MULTIPLIER ARCHITECTURE/

A hybrid radix-4/radix-8 architecture targeted for high bit, general p urpose, digital multipliers is presented as a compromise between the h igh speed of a radix-4 multiplier architecture and the low power dissi pation of a radix-8 multiplier architecture, In this hybrid radix-4/ra dix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the multiplicand for use in generating the radix-8 partial product, is performed in parallel with the reduction of the radix-4 partial products rather than serially, a s in a radix-8 multiplier, This hybrid radix-4/radix-8 multiplier arch itecture requires 13% less power for a 64 x 64-b multiplier, and resul ts in only a 9% increase in delay, as compared with a radix-4 implemen tation, When the voltage supply is scaled to equalize delay, the 64 x 64-b hybrid multiplier dissipates less power than either the radix-4 o r radix-8 multipliers. The hybrid radix-4/radix-8 architecture is ther efore appropriate for those applications that must dissipate minimal p ower while operating at high speeds.