ENHANCED DEGRADATION DURING STATIC STRESSING OF A METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR EMBEDDED IN A CIRCUIT

We have observed a unique phenomenon during low-gate voltage (V-G) sta tic stressing of metal-oxide-semiconductor-field-effect-transistors (M OSFETs). Static stressing has been performed by probing n-MOSFET devic es that are discrete, as well as devices that are embedded in a circui t, Although the measured substrate current for the circuit and discret e devices is similar; significantly more hole trapping is observed und er low-V-G static stressing of circuit devices. It is clear that the e xtent of hole trapping is circuit dependent and that in actual operati on the devices will not undergo such static stressing. Nevertheless, t hese devices provided a unique opportunity to study the role oi hole t rapping in interface-state formation. Thus, rather than identifying th e cause for increased hole trapping, we focused our efforts on underst anding the mechanisms of interface-state formation. It is found that w hile both electrons and holes are needed for the formation of interfac e states, it is hole trapping that is the rate-limiting factor in devi ce degradation.