PERFORMANCE AND RELIABILITY TRADE-OFF OF LARGE-TILTED-ANGLE IMPLANT P-POCKET ON STACKED-GATE MEMORY DEVICES

In this paper, the effects of large-tilted-angle p-pocket (LAP) implan tation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 4 5 degrees LAP cell featuring a fastest programming speed, however, wou ld not be desirable due to the seriously aggravated read current degra dation, drain/read disturbance, and early snap-back breakdown. The cel ls with 0 degrees and 30 degrees tilted angle are the feasible cells w ith the moderate programming performance and acceptable reliability co nstraints. Furthermore, the 0 degrees LAP cell is preferred for the fa ct that it exhibits the desirable read current than that in 30 degrees cell. Based on the cell performance and reliability consideration, th e 0 degrees p-pocket implanted cell is the optimal angle among 0 degre es; 30 degrees and 45 degrees for the future scaling of stacked-gate m emory cell.