METALLIC IMPURITY GETTERING AND SECONDARY DEFECT FORMATION IN MEGAELECTRON VOLT SELF-IMPLANTED CZOCHRALSKI AND FLOAT-ZONE SILICON

Citation
Ra. Brown et al., METALLIC IMPURITY GETTERING AND SECONDARY DEFECT FORMATION IN MEGAELECTRON VOLT SELF-IMPLANTED CZOCHRALSKI AND FLOAT-ZONE SILICON, Journal of the Electrochemical Society, 144(8), 1997, pp. 2872-2881
Citations number
76
Categorie Soggetti
Electrochemistry
ISSN journal
00134651
Volume
144
Issue
8
Year of publication
1997
Pages
2872 - 2881
Database
ISI
SICI code
0013-4651(1997)144:8<2872:MIGASD>2.0.ZU;2-N
Abstract
Megaelectron volt (MeV) self-implantation has been investigated as a m eans of producing buried defect layers for gettering metallic impuriti es in Czochralski (CZ) and float-zone (FZ) silicon. The properties of implanted and annealed wafers were studied by generation lifetime (Zer bst) analysis of transient capacitance data, capacitance-voltage measu rements, deep-level transient spectroscopy, scanning electron-beam-ind uced current microscopy, transmission electron microscopy, optical mic roscopy with preferential chemical etching, and secondary ion mass spe ctroscopy. We found that metallic contaminants such as Fe and Cu were effectively gettered to buried extended defect layers formed by implan tation of ion fluences less than or similar to 1 x 10(15) Si cm(-2). F or example, the concentration of iron in regions near the buried defec ts can be reduced to below 10(10) cm(-3) in samples annealed at 900 de grees C. The region above the damage layer appears to be free of elect rically active defects, having very high generation lifetime values, a nd is therefore suitable for device processing. However, the structure and width of the buried defect band is sensitive to the implanted ion fluence and the oxygen content of the wafers. For example, the defect layers formed by high ion fluences (similar to 10(15) cm(-2)) are wid er in FZ wafers than in CZ wafers. For fluences approximate to 1 x 10( 14) cm(2), dislocations extend from the buried damage band in both dir ections during annealing and are observed at depths up to 10 mu m. The se dislocations intersect the wafer surface in both CZ and FZ wafers, making fluences lower than similar or equal to 5 x 10(14) cm(-2) unsui table for device fabrication.