A REGULAR FOLDING PROCEDURE

Folding transformations on processor arrays result in smaller processo r arrays, more efficient work for the processing elements! a decrease in I/O time, pipelineable implementations and circular data flow are p resented in [1]. In this paper the folding transformation is defined v ia symmetric linear transformations and interlocking translations impl emented on the space time graphs. The regular folding transformation a ccording to a translated line of symmetry offers valid and regular sol utions. Two generalized procedures for regular folding are given here keep the complexity of the data communications, the processor operatio ns, the regular data flow and avoid data collision. The matrix vector multiplication algorithm is given as an example of the proposed proced ures and the best folding transformation is determined. The efficiency analysis shows that the implementation obtained utilizes the processo r array with double efficiency. Moreover, by using the same processor array, problems with double the dimension can be solved. Also, the cir cular data flow can be used for cascaded algorithms.