PERFORMANCE OF THE NEW ATM SWITCH FOR B-ISDN

In this paper a new N x N space division ATM switch architecture based on banyan network is presented. This architecture is a multistage int erconnection network with more than n (n = log(2) N) switching stages. The interconnection algorithm offers many access outputs and resolves output contention by laying buffers. The paper analyzes the switching performance and shows that this switch has lower cell loss probabilit y vs. buffer size than other two known solutions given in (Tobagi et a l., 1991; Urushidani, 1991; Hino et al., 1995).