A BALANCED-MESH CLOCK ROUTING TECHNIQUE FOR PERFORMANCE IMPROVEMENT

This paper presents a clock routing technique called Balanced-Mesh Met hod (BMM) which incorporates the advantages of two famous conventional -clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock si gnal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In B MM, the clock net is routed as a set of relatively small meshes of int erconnects driven by relatively small buffers. Each mesh covers an are a called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected b y a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circ uit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routi ng program that provides each mesh routing and the tree routing connec ting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210 ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional metho ds.