DELAY AND POWER EXPRESSIONS FOR A CMOS INVERTER DRIVING A RESISTIVE-CAPACITIVE LOAD

A delay and power model of a CMOS inverter driving a resistive-capacit ive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and a nalyze those CMOS inverters that drive a large RC load when considerin g both speed and power. Expressions are provided for estimating the pr opagation delay and transition time which exhibit less than 27% discre pancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS in verter driving a resistive-capacitive interconnect line which are accu rate to within 15% of SPICE for most practical loads.