ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH

Nowadays, metastability is becoming a serious problem in high-performa nce VLSI design, mainly due to the relatively-high probability of erro r when a bistable circuit operates at high frequencies. As far as we k now, there is not any work published that justifies and formally chara cterizes metastable behavior in dynamic latches. With current technolo gies, dynamic latches are widely used in high-performance VLSI circuit s, mainly due to their lower cost and higher operation speed than stat ic latches. In this work, we demonstrate that dynamic memory cells pre sent an anomalous behavior referred to as metastable operation with ch aracteristics similar to those of static latches. We perform a suitabl e generalization of metastability to the dynamic case, applying it to a CMOS dynamic D-latch. A theoretical model will be proposed, allowing the quantification of metastability, and it will be validated through electric simulation with HSPICE. After that, we have compared the met astable behavior of the dynamic latch with its static counterpart, obt aining results about the characteristic parameters of metastability an d the Mean Time Between Failures (MTBF) for both kinds of bistable cir cuits. These results have allowed us to conclude that, unlike metastab ility windows in static latches, a clearly defined input interval exis ts which produces an infinite resolution time. Regarding MTBE the dyna mic latch presents a very low MTBF value compared to the static latch. These results show that dynamic latches should not be used in those c ircuits where the risk of asynchronism between clock and data signals is not negligible.