DESIGN FOR TESTABILITY USING STATE DISTANCES

The average distance between states is proposed as a new testability m easure for finite state machines (FSMs). Also proposed is the concept of center state to reduce distances in FSMs. This test function embedd ing technique has been shown to improve the testability of sequential circuits with minimal overhead. An overview of several design-for-test ability (DFT) and synthesis-for-testability (SFT) methods for sequenti al circuits will also be given in this paper. Experimental results hav e shown that the DFT approach is more advantageous than the SFT approa ch to implement our test function. The contribution of this paper is t o analyze the trade-offs between several aspects of DFT and SFT techni ques.