REALIZATIONS OF PARALLEL AND MULTIBIT PARALLEL SHIFT REGISTER GENERATORS

In this paper, we consider how to realize the parallel shift register generators (PSRG) and mutibit PSRG's, which can be directly used for p arallel frame synchronous scrambling (FSS) in the bit-and multibit-int erleaved multiplexing environments, We first describe the structure of PSRG's in terms of three parameters-the state transition matrix, the initial state vector, and the generating vectors, Then we discuss how to determine the three parameters of PSRG's that generate the desired parallel sequences in general, We further develop the method for the r ealization of minimum length PSRG's, and then for the realization of P SRG's with minimized circuit complexity, Finally, we consider how to r ealize minimal PSRG's for use in multibit-parallel scrambling, The res ults are summarized in four sets of theorems, and are demonstrated thr ough four examples.