At high user densities, FDTS/DF tau=2 can be efficiently implemented a
s a 3D-110 detector. The simplicity of the detector facilitates parall
el implementations that nearly double the data rate. This high speed v
ersion is derived from the sample rate version and enhanced to elimina
te the need for cascaded analog sample-and-holds. By factoring out a 1
+D term, the number of input terms to the detector summing nodes is re
duced to two, providing improved speed for a digital circuit.