NOVEL SPIN-VALVE MEMORY ARCHITECTURE

Giant magnetoresistance (GMR) materials are used for random access, no n-volatile memories. Different memory architectures have been proposed , both using GMR multilayers and spin-valve (SV) sandwich structures, In most of these approaches extra word lines are needed for writing pu rposes in addition to read contacts. This makes three interconnect lev els. We show results on a simpler SV memory architecture, where writin g is achieved using the read current contacts. This is relevant in ter ms of fabrication, as only two interconnecting layers are necessary to address a matrix of bits. A 400 bit memory matrix was fabricated and tested. A 2 mV signal between ''0'' and ''1'' states was measured for a bit inside this matrix.