THE ARCHITECTURE OF A HIGHLY RECONFIGURABLE RISC DATA-FLOW ARRAY PROCESSOR

The architectural design and VLSI implementation of a highly reconfigu rable dataflow RISC (DF-RISC) processing element (PE) are presented. T his processor forms an element of a processor array (DF-RISC-PA) which possesses the features of both static and dynamic dataflow models. Th e array can be programmed to execute arbitrary algorithms (recursive o r irregular) in both static and dynamic manner. The processor array is modelled at the behavioural level in VHDL. The gate level implementat ion and VLSI layout of both the PE and the array are obtained with the help of OASIS Silicon compiler by translating the VHDL model to Logic 3. Sample computations are mapped to illustrate functionality, The des ign is validated at all levels of abstraction. The results of simulati on of the PE array are presented. The architecture is compared with pr evious approaches. The prototype PE requires 4261 CMOS gates and uses an area of 7512 x 8081 mu m(2).