NOVEL ARCHITECTURE FOR 2-DIMENSIONAL HIGH-THROUGHPUT RATE REAL-TIME DISCRETE COSINE TRANSFORM AND THE VLSI DESIGN

The discrete cosine transform (DCT) has been widely used as the core o f digital image and video signal compression. However, its computation is so intensive and it is important to meet the requirement for high speed. A novel architecture of the VLSI design of a 2D DCT has been de veloped. This architecture contains the following features: use of the programmable logic array (PLA) to replace multipliers; overlapped row -column operations and pipeline structure to reduce the total computat ion time; and highly modular and regular structure for the efficient V LSI implementation. This architecture is implemented to a 8x8 2D DCT. The circuit is designed by UMC's 0.8 mu m SPDM CMOS process and the ce ll library is provided by ITRI CCL. The simulation is shown that the s peed of the data processing for this DCT is more than 50 MHz. It perfo rms equivalently 800 million multiplications and accumulations per sec ond.