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Results:
1-25
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Results: 25
Authors:
Christen, E
Bakalar, K
Citation: E. Christen et K. Bakalar, Library development using the VHDL-AMS language, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 5-16
Authors:
Schwarz, P
Haase, J
Citation: P. Schwarz et J. Haase, Behavioral modeling of complex heterogeneous microsystems, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 17-30
Authors:
Aubert, V
Sabiro, SG
Citation: V. Aubert et Sg. Sabiro, VHDL-AMS, a unified language to describe Multi-Domain, Mixed-Signal designs. Mechatronic applications, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 31-42
Authors:
Dabrowski, J
Pulka, A
Citation: J. Dabrowski et A. Pulka, Efficient modeling of analog and mixed A/D systems via piece-wise linear technique, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 43-54
Authors:
Ashenden, PJ
Wilsey, PA
Martin, DE
Citation: Pj. Ashenden et al., SUAVE: Object-oriented and genericity extensions to VHDL for high-level modeling, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 57-70
Authors:
Radetzki, M
Nebel, W
Citation: M. Radetzki et W. Nebel, Digital circuit design with objective VHDL, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 71-84
Authors:
Fernandez, LS
Pickin, S
Groba, A
Madrid, NM
Alonso, A
Citation: Ls. Fernandez et al., UF: Architecture and semantics for system-level multiformalism descriptions, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 89-98
Authors:
de Araujo, CC
Barros, E
Citation: Cc. De Araujo et E. Barros, Automatic interface generation among VHDL processes in hardware/software co-design, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 99-110
Authors:
Cloute, F
Contensou, JN
Esteve, D
Pampagnin, P
Pons, P
Favard, Y
Citation: F. Cloute et al., System-level specification and architecture exploration: an avionics codesign application, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 111-120
Authors:
Kumar, R
Citation: R. Kumar, Using SDL to model reactive embedded system in a co-design environment, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 121-130
Authors:
Ploger, PG
Budde, R
Sylla, KH
Citation: Pg. Ploger et al., A synchronous object-oriented design flow for embedded applications, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 131-142
Authors:
Bjureus, P
Jantsch, A
Citation: P. Bjureus et A. Jantsch, Heterogeneous system-level cosimulation with SDL and Matlab, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 145-157
Authors:
Moser, V
Boegli, A
Amann, HP
Pellandini, F
Citation: V. Moser et al., VHDL-based HW/SW cosimulation of microsystems, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 159-168
Authors:
Bauer, M
Ecker, W
Zinn, A
Citation: M. Bauer et al., Modeling interrupts for HW/SW co-simulation based on a VHDL/C coupling, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 169-178
Authors:
Jantsch, A
Kumar, S
Sander, I
Svantesson, B
Oberg, J
Hemani, A
Ellervee, P
O'Nils, M
Citation: A. Jantsch et al., A comparison of six languages for system level description of telecom applications, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 181-192
Authors:
Cook, F
Messer, N
Carpenter, A
Citation: F. Cook et al., High level modelling in SDL and VHDL, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 193-203
Authors:
Berry, G
Harcourt, E
Lavagno, L
Sentovich, E
Citation: G. Berry et al., ECL: A specification environment for system-level design, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 205-212
Authors:
Pasquier, O
Muller, F
Calvez, JP
Heller, D
Chenard, D
Citation: O. Pasquier et al., The MCSE approach for system-level design, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 213-224
Authors:
Corvino, D
Epicoco, I
Ferrandi, F
Fummi, F
Sciuto, D
Citation: D. Corvino et al., Automatic VHDL restructuring for RTL synthesis optimization and testability improvement, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 227-238
Authors:
Albenge, MF
Houzet, D
Citation: Mf. Albenge et D. Houzet, VHDL dynamic loop synthesis, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 239-247
Authors:
Williams, AC
Brown, AD
Baidas, ZA
Citation: Ac. Williams et al., Hierarchical module expansion in a VHDL behavioural synthesis system, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 249-260
Authors:
Nicolae, AF
Cerny, E
Citation: Af. Nicolae et E. Cerny, Port-stitching: An interface-oriented hardware specification and VHDL model generation, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 263-272
Authors:
Borrione, D
Georgelin, P
Citation: D. Borrione et P. Georgelin, Formal verification of VHDL using VHDL-like ACL2 models, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 273-284
Authors:
Allara, A
Bombana, M
Comai, S
Josko, B
Schlor, R
Sciuto, D
Citation: A. Allara et al., Specification of embedded monitors for property checking, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 285-294
Authors:
Drogehorn, O
Hummer, HD
Geisselhardt, W
Citation: O. Drogehorn et al., Formal specification and verification of transfer-protocols for system-design in VHDL - Practiced on a sliding-window-protocol, ELECTRONIC CHIPS & SYSTEMS DESIGN LANGUAGES, 2001, pp. 295-306
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