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Results: 1-25/306
Authors:
WU CK
DAWSON E
Citation: Ck. Wu et E. Dawson, GENERALIZED INVERSES IN PUBLIC-KEY CRYPTOSYSTEM DESIGN, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 321-326
Authors:
CHIKOUCHE D
BEKKA RE
Citation: D. Chikouche et Re. Bekka, CYLINDRICAL ARCHITECTURES FOR 1-D RECURSIVE DIGITAL-FILTERS - A STATE-SPACE APPROACH, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 327-332
Authors:
CHANG LC
TON LR
KAO MF
CHUNG CP
Citation: Lc. Chang et al., STACK OPERATIONS FOLDING IN JAVA PROCESSORS, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 333-340
Authors:
KRISHNA CM
Citation: Cm. Krishna, MEMORY ALIGNMENT ISSUES IN REAL-TIME SYSTEMS, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 341-346
Authors:
CHANG CH
FALKOWSKI BJ
Citation: Ch. Chang et Bj. Falkowski, LOGICAL MANIPULATIONS AND DESIGN OF TRIBUTARY NETWORKS IN THE ARITHMETIC SPECTRAL-DOMAIN, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 347-356
Authors:
THEODORIDIS G
THEOHARIS S
SOUDRIS D
GOUTIS CE
Citation: G. Theodoridis et al., METHOD FOR MINIMIZING THE SWITCHING ACTIVITY OF 2-LEVEL LOGIC-CIRCUITS, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 357-363
Authors:
WANG L
CHEN X
ALMAINI AEA
Citation: L. Wang et al., ALGEBRAIC PROPERTIES OF MULTIPLE-VALUED MODULE SYSTEMS AND THEIR APPLICATIONS TO CURRENT-MODE CMOS CIRCUITS, IEE proceedings. Computers and digital techniques, 145(5), 1998, pp. 364-368
Authors:
PARK S
LEE G
Citation: S. Park et G. Lee, PARTIAL SCAN DESIGN BASED ON LEVELLISED COMBINATIONAL STRUCTURE, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 249-254
Authors:
LU NP
CHUNG CP
Citation: Np. Lu et Cp. Chung, PARALLELISM EXPLOITATION IN SUPERSCALAR MULTIPROCESSING, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 255-264
Authors:
KOC CK
HUNG CY
Citation: Ck. Koc et Cy. Hung, FAST ALGORITHM FOR MODULAR REDUCTION, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 265-271
Authors:
GUO JH
WANG CL
Citation: Jh. Guo et Cl. Wang, HARDWARE-EFFICIENT SYSTOLIC ARCHITECTURE FOR INVERSION AND DIVISION IN GF(2(M)), IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 272-278
Authors:
WANG CC
TSAI CF
LEE JP
Citation: Cc. Wang et al., ANALYSIS OF RADIX SEARCHING OF EXPONENTIAL BIDIRECTIONAL ASSOCIATIVE MEMORY, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 279-285
Authors:
YANG MH
LEE JW
KANG S
Citation: Mh. Yang et al., EFFICIENT ALGORITHM AND ARCHITECTURE FOR SCAN CONVERSION IN HDTV, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 287-291
Authors:
JIA W
ZHAO W
Citation: W. Jia et W. Zhao, FAULT-TOLERANT SCALEABLE MULTICAST ALGORITHM WITH PIGGYBACKING APPROACH ON LOGICAL PROCESS RING, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 292-300
Authors:
JOU JY
CHOU DS
Citation: Jy. Jou et Ds. Chou, SENSITISABLE-PATH-ORIENTED CLUSTERED VOLTAGE SCALING TECHNIQUE FOR LOW-POWER, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 301-307
Authors:
GIL C
ORTEGA J
Citation: C. Gil et J. Ortega, ALGEBRAIC TEST-PATTERN GENERATION BASED ON THE REED-MULLER SPECTRUM, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 308-316
Authors:
OH JH
MOON SJ
Citation: Jh. Oh et Sj. Moon, MODULAR MULTIPLICATION METHOD, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 317-318
Authors:
YAN JT
Citation: Jt. Yan, CORRESPONDENCE ON PLANAR CONSTRAINED TERMINALS OVER-THE-CELL ROUTER, IEE proceedings. Computers and digital techniques, 145(4), 1998, pp. 319-320
Authors:
HARRISON J
Citation: J. Harrison, HARDWARE SOFTWARE CODESIGN FOR EMBEDDED SYSTEMS/, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 153-153
Authors:
BENMOHAMMED M
RAHMOUNE A
Citation: M. Benmohammed et A. Rahmoune, AUTOMATIC-GENERATION OF REPROGRAMMABLE MICROCODED CONTROLLERS WITHIN A HIGH-LEVEL SYNTHESIS ENVIRONMENT, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 155-160
Authors:
DEEGENER M
HUSS SA
Citation: M. Deegener et Sa. Huss, DESIGN SPACE EXPLORATION TECHNIQUES FOR THE CODESIGN OF EMBEDDED DATA-PROCESSING SYSTEMS, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 161-170
Authors:
ESSER R
TEICH J
THIELE L
Citation: R. Esser et al., CODESIGN - AN EMBEDDED SYSTEM-DESIGN ENVIRONMENT, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 171-180
Authors:
MARCHIORO GF
DAVEAU JM
ISMAIL TB
JERRAYA AA
Citation: Gf. Marchioro et al., TRANSFORMATIONAL PARTITIONING FOR CODESIGN, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 181-195
Authors:
HOU J
WOLF W
Citation: J. Hou et W. Wolf, PRESYNTHESIS PARTITIONING FOR HARDWARE SOFTWARE COSYNTHESIS/, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 197-202
Authors:
HU X
GREENWOOD G
Citation: X. Hu et G. Greenwood, EVOLUTIONARY APPROACH TO HARDWARE SOFTWARE PARTITIONING/, IEE proceedings. Computers and digital techniques, 145(3), 1998, pp. 203-209