METHOD FOR MINIMIZING THE SWITCHING ACTIVITY OF 2-LEVEL LOGIC-CIRCUITS

A new approach for implementing two-level logic circuits, which exhibi t minimal power dissipation, is introduced. Switching activity reducti on of the logic network nodes is achieved by inserting additional inpu t signals in specific gates. Based on the statistical properties (i.e. static and transition probabilities) of the primary inputs, a new con cept for grouping the input variables with similar features is present ed. An efficient synthesis algorithm for generating the set of all cla sses of the variables, and solving the minimum covering problem for ea ch class is developed. A comparison of the results produced by the pro posed method, and those from ESPRESSO, shows that substantial power re duction can be achieved.