AAAAAA

   
Results: 1-2 |
Results: 2
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield
Authors: Noda, K Takeda, K Matsui, K Ito, S Masuoka, S Kawamoto, H Ikezawa, N Aimoto, Y Nakamura, N Iwasaki, T Toyoshima, H Horiuchi, T
Citation: K. Noda et al., An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield, IEEE J SOLI, 36(3), 2001, pp. 510-515
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro
Authors: Takeda, K Aimoto, Y Nakamura, N Toyoshima, H Iwasaki, T Noda, K Matsui, K Itoh, S Masuoka, S Horiuchi, T Nakagawa, A Shimogawa, K Takahashi, H
Citation: K. Takeda et al., A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro, IEEE J SOLI, 35(11), 2000, pp. 1631-1640
Risultati: 1-2 |