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Results: 1-3 |
Results: 3
FPGA-based SAT solver architecture with near-zero synthesis and layout overhead
Authors: Zhong, P Martonosi, M Ashar, P
Citation: P. Zhong et al., FPGA-based SAT solver architecture with near-zero synthesis and layout overhead, IEE P-COM D, 147(3), 2000, pp. 135-141
An edge-endpoint-based configurable hardware architecture for VLSI layout Design Rule Checking
Authors: Luo, Z Martonosi, M Ashar, P
Citation: Z. Luo et al., An edge-endpoint-based configurable hardware architecture for VLSI layout Design Rule Checking, VLSI DESIGN, 10(3), 2000, pp. 249-263
Using configurable computing to accelerate Boolean satisfiability
Authors: Zhong, PX Martonosi, M Ashar, P Malik, S
Citation: Px. Zhong et al., Using configurable computing to accelerate Boolean satisfiability, IEEE COMP A, 18(6), 1999, pp. 861-868
Risultati: 1-3 |