Citation: Tm. Burks et al., CRITICAL PATHS IN CIRCUITS WITH LEVEL-SENSITIVE LATCHES, IEEE transactions on very large scale integration (VLSI) systems, 3(2), 1995, pp. 273-291
Authors:
SAKALLAH KA
MUDGE TN
BURKS TM
DAVIDSON ES
Citation: Ka. Sakallah et al., SYNCHRONIZATION OF PIPELINES, IEEE transactions on computer-aided design of integrated circuits and systems, 12(8), 1993, pp. 1132-1146