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Results: 1
Switching activity evaluation of CMOS digital circuits using logic timing simulation
Authors:
Juan-Chico, J Bellido, MJ Ruiz-de-Clavijo, P Baena, C Jimenez, CJ Valencia, M
Citation:
J. Juan-chico et al., Switching activity evaluation of CMOS digital circuits using logic timing simulation, ELECTR LETT, 37(9), 2001, pp. 555-557
Risultati:
1-1
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