Authors:
Louis, D
Beverina, A
Arvet, C
Lajoinie, E
Peyne, C
Holmes, D
Maloney, D
Citation: D. Louis et al., Cleaning status on low-k dielectric in advanced VLSI interconnect: Characterisation and principal issues, MICROEL ENG, 57-8, 2001, pp. 621-627
Authors:
Torres, J
Palleau, J
Tardiff, F
Bernard, H
Beverina, A
Motte, P
Pantel, R
Juhel, M
Citation: J. Torres et al., Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology, MICROEL ENG, 50(1-4), 2000, pp. 425-431