Authors: Restle, PJ McNamara, TG Webber, DA Camporese, PJ Eng, KF Jenkins, KA Allen, DH Rohn, MJ Quaranta, MP Boerstler, DW Alpert, CJ Carter, CA Bailey, RN Petrovick, JG Krauter, BL McCredie, BD

Citation: Pj. Restle et al., A clock distribution network for microprocessors, IEEE J SOLI, 36(5), 2001, pp. 792-799

Authors: Boerstler, DW

Citation: Dw. Boerstler, A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz, IEEE J SOLI, 34(4), 1999, pp. 513-519